Thevenin termination why

This is possible because of the following:. The foregoing discussion raises some interesting points. In order to use series-terminated logic in a bus organized system, it is necessary to reduce the system size as the clock frequency increases. This minimizes the dead time. At clock frequencies above MHz, it becomes difficult to build meaningful systems of this kind.

So, how is it possible supercomputers with clock frequencies over a GHz work? If we assume that the EM energy is absorbed at the load end of the line by placing a termination there as shown in Figure 5, the events in the first part of the operations are the same as all of the previous examples.

Figure 6 depicts this for both the rising and the falling edges. There are the same waveforms at all points along the transmission line. The logic 1 in Figure 6 does not reach this level. Even though there are no reflections, the circuit will not work, so something must be done to raise the logic 1 level.

The divider formed by the output impedance and the line impedance set the logic 1 level. One of these factors needs to change. It is difficult to change line impedances enough to remedy this problem so the driver output impedance needs to be reduced. Figure 7 depicts this. A new driver has been located with an output impedance of 5 ohms. This time the circuit has a 3. This is a proper logic level 1 for this circuit. All of the conditions have been met and there are no illegal logic states.

In addition, a load can be placed anywhere along a transmission line with the assurance that it will always see a proper logic signal. This is called a parallel termination. It is the terminating method used for all very high speed logic paths. However, this signaling protocol also has its drawbacks in terms of power consumption. With the 3. Because of this, the signal swings of all logic families intended to be implemented for parallel termination are small.

The foregoing low level logic families work very well at high speeds. But, due to the small signal swings, they do not have a very big noise margin. As a result, noise management becomes a very important part of the design process. This is especially true when there is a mixed logic system that contains 3. In order to create a logic 1 voltage that is large enough for proper operation, the output impedance of the driver must be much less than the line impedance.

In addition to series terminations and parallel terminations, sometimes other terminations are offered up as solutions to reflections. Those terminations include:. AC terminations are sometimes suggested as a way to control the voltage doubling at the open end of a transmission line. An AC termination attaches the parallel terminating resistor to the end of a net with a small capacitor. When an AC termination is attached to the end of a net, the result is a rising or a falling edge that has an RC time constant that effectively slows down the edge while it limits overshoot.

If the edge degradation is acceptable, an AC termination might be the way to cope with fast edges. In Figure 8, the upper portion of the figure shows the same circuit contained in Figure 1 but with an AC termination. If the clock frequency is increased much beyond the 66 MHz in this example, not only does the waveform become more like a sine wave rather than a square wave, it is no longer capable of maintaining the required signal swing.

Diode terminations at the receiver end of a transmission line in lieu of a resistor termination are another instance of a band-aid approach. Instead of designing transmission lines with proper terminations that prevent overshoot from becoming excessive, a pair of diodes is attached between the signal line and the two power rails and is oriented such that when overshoot exceeds Vdd, one diode turns on as a clamp.

This is shown in Figure 9. When the overshoot attempts to go below Vss Voltage source supply , the other diode turns on as a clamp. This does work however the diodes must be Shottky diodes in order to turn on quickly enough. In addition, the cost per line of this particular approach is quite high.

Parallel terminations described thus far have been connected to ground. This is a symbolic ground as the actual parallel terminations always connect to a special terminator voltage not ground, Vdd Voltage drain or Vee Voltage emitter.

In the case of ECL, which operates between ground and When using the above-mentioned logic families, it is necessary to add a power supply and a power plane to supply the needed terminator voltages. If there are only a few circuits that need parallel terminations, as is the case when PECL is used for an interface to a transceiver, this equates to a large expense for just a few lines.

Another approach to this problem is to use a two-resistor network to emulate the terminator impedance and the terminator voltage. This is referred to as a Thevenin equivalent and it is depicted in Figure To determine the values of the resistors required to create the equivalent voltage and impedance, it is necessary to solve the two equations featured in this figure.

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Post as a guest Name. Email Required, but never shown. While both the resistors could function as a pull-up or pull-down for the signal, Thevenin termination results in constant draining of current on regardless of the state of the driver.

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Common PCB Trace Termination Techniques There are a few termination techniques that you can use to ensure high-speed signals on your PCB suffer from no reflection or distortion on the trace. Series Termination The series termination is an often-used technique.